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145
HARDWARE/NAND/nand.h
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145
HARDWARE/NAND/nand.h
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#ifndef _NAND_H
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#define _NAND_H
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#include "sys.h"
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//////////////////////////////////////////////////////////////////////////////////
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>ѧϰʹ<CFB0>ã<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κ<EFBFBD><CEBA><EFBFBD>;
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//ALIENTEK STM32<33><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//NAND FLASH <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:2016/1/15
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//<2F>汾<EFBFBD><E6B1BE>V1.5
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//<2F><>Ȩ<EFBFBD><C8A8><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ؾ<EFBFBD><D8BE><EFBFBD>
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//Copyright(C) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾ 2014-2024
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//All rights reserved
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//********************************************************************************
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//<2F><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5>
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//V1.1 20160520
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//1,<2C><><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>ECC֧<43><D6A7>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>NAND_ECC_SECTOR_SIZE<5A><45>СΪ<D0A1><CEAA>λ<EFBFBD><CEBB><EFBFBD>ж<EFBFBD>дʱ<D0B4><CAB1><EFBFBD><EFBFBD>)
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//2,<2C><><EFBFBD><EFBFBD>NAND_Delay<61><79><EFBFBD><EFBFBD>,<2C><><EFBFBD>ڵȴ<DAB5>tADL/tWHR
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//3,<2C><><EFBFBD><EFBFBD>NAND_WritePageConst<73><74><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѱ<EFBFBD><D1B0><EFBFBD><EFBFBD>.
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//V1.2 20160525
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//1,ȥ<><C8A5>NAND_SEC_SIZE<5A>궨<EFBFBD>壬<EFBFBD><E5A3AC>NAND_ECC_SECTOR_SIZE<5A><45><EFBFBD><EFBFBD>
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//2,ȥ<><C8A5>nand_dev<65>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>secbufָ<66>룬<EFBFBD>ò<EFBFBD><C3B2><EFBFBD>
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//V1.3 20160907
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//1,<2C><><EFBFBD><EFBFBD>NAND_TADL_DELAY<41><59>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>tADL<44><4C><EFBFBD>ӳ<EFBFBD>ʱ<EFBFBD><CAB1>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//V1.4 20180321
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//1,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>H27U4G8F2EоƬ<D0BE><C6AC>֧<EFBFBD><D6A7>
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//2,<2C><EFBFBD>MEMSET/MEMHOLD/MEMHIZ<49><5A><EFBFBD><EFBFBD>ʱ,<2C><>֧<EFBFBD><D6A7>H27U4G08F2E.
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//V1.5 20180531
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//1.<2E><><EFBFBD><EFBFBD>NAND_TWHR_DELAY/NAND_TRHW_DELAY/NAND_TPROG_DELAY/NAND_TBERS_DELAY<41>ĸ<EFBFBD><C4B8><EFBFBD>ʱ,<2C><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>
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//2.<2E><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ms<6D><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>ʱ<EFBFBD>䲻<EFBFBD><E4B2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD>ɳ<EFBFBD><C9B3><EFBFBD>
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//////////////////////////////////////////////////////////////////////////////////
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#define NAND_MAX_PAGE_SIZE 4096 //<2F><><EFBFBD><EFBFBD>NAND FLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PAGE<47><45>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPARE<52><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC>4096<39>ֽ<EFBFBD>
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#define NAND_ECC_SECTOR_SIZE 512 //ִ<><D6B4>ECC<43><43><EFBFBD><EFBFBD><EFBFBD>ĵ<EFBFBD>Ԫ<EFBFBD><D4AA>С<EFBFBD><D0A1>Ĭ<EFBFBD><C4AC>512<31>ֽ<EFBFBD>
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//NAND FLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
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#define NAND_TADL_DELAY 30 //tADL<44>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>70ns
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#define NAND_TWHR_DELAY 25 //tWHR<48>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>60ns
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#define NAND_TRHW_DELAY 35 //tRHW<48>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>100ns
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#define NAND_TPROG_DELAY 200 //tPROG<4F>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>ֵ200us,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ700us
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#define NAND_TBERS_DELAY 4 //tBERS<52>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>ֵ3.5ms,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ10ms
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//NAND<4E><44><EFBFBD>Խṹ<D4BD><E1B9B9>
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typedef struct
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{
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u16 page_totalsize; //ÿҳ<C3BF>ܴ<EFBFBD>С<EFBFBD><D0A1>main<69><6E><EFBFBD><EFBFBD>spare<72><65><EFBFBD>ܺ<EFBFBD>
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u16 page_mainsize; //ÿҳ<C3BF><D2B3>main<69><6E><EFBFBD><EFBFBD>С
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u16 page_sparesize; //ÿҳ<C3BF><D2B3>spare<72><65><EFBFBD><EFBFBD>С
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u8 block_pagenum; //ÿ<><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD>
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u16 plane_blocknum; //ÿ<><C3BF>plane<6E><65><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD><EFBFBD>
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u16 block_totalnum; //<2F>ܵĿ<DCB5><C4BF><EFBFBD><EFBFBD><EFBFBD>
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u16 good_blocknum; //<2F>ÿ<EFBFBD><C3BF><EFBFBD><EFBFBD><EFBFBD>
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u16 valid_blocknum; //<2F><>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<28><><EFBFBD>ļ<EFBFBD>ϵͳʹ<CDB3>õĺÿ<C4BA><C3BF><EFBFBD><EFBFBD><EFBFBD>)
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u32 id; //NAND FLASH ID
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u16 *lut; //LUT<55><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DFBC><EFBFBD>-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>
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u32 ecc_hard; //Ӳ<><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ECCֵ
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u32 ecc_hdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];//ECCӲ<43><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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u32 ecc_rdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];//ECC<43><43>ȡ<EFBFBD><C8A1>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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}nand_attriute;
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extern nand_attriute nand_dev; //nand<6E><64>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9>
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#define NAND_RB PDin(6) //NAND Flash<73><68><EFBFBD><EFBFBD>/æ<><C3A6><EFBFBD><EFBFBD>
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#define NAND_ADDRESS 0X80000000 //nand flash<73>ķ<EFBFBD><C4B7>ʵ<EFBFBD>ַ,<2C><>NCE3,<2C><>ַΪ:0X8000 0000
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#define NAND_CMD 1<<16 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#define NAND_ADDR 1<<17 //<2F><><EFBFBD>͵<EFBFBD>ַ
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//NAND FLASH<53><48><EFBFBD><EFBFBD>
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#define NAND_READID 0X90 //<2F><>IDָ<44><D6B8>
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#define NAND_FEATURE 0XEF //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
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#define NAND_RESET 0XFF //<2F><>λNAND
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#define NAND_READSTA 0X70 //<2F><>״̬
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#define NAND_AREA_A 0X00
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#define NAND_AREA_TRUE1 0X30
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#define NAND_WRITE0 0X80
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#define NAND_WRITE_TURE1 0X10
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#define NAND_ERASE0 0X60
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#define NAND_ERASE1 0XD0
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#define NAND_MOVEDATA_CMD0 0X00
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#define NAND_MOVEDATA_CMD1 0X35
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#define NAND_MOVEDATA_CMD2 0X85
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#define NAND_MOVEDATA_CMD3 0X10
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//NAND FLASH״̬
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#define NSTA_READY 0X40 //nand<6E>Ѿ<EFBFBD><EFBFBD><D7BC><EFBFBD><EFBFBD>
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#define NSTA_ERROR 0X01 //nand<6E><64><EFBFBD><EFBFBD>
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#define NSTA_TIMEOUT 0X02 //<2F><>ʱ
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#define NSTA_ECC1BITERR 0X03 //ECC 1bit<69><74><EFBFBD><EFBFBD>
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#define NSTA_ECC2BITERR 0X04 //ECC 2bit<69><74><EFBFBD>ϴ<EFBFBD><CFB4><EFBFBD>
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//NAND FLASH<53>ͺźͶ<C5BA>Ӧ<EFBFBD><D3A6>ID<49><44>
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#define MT29F4G08ABADA 0XDC909556 //MT29F4G08ABADA
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#define MT29F16G08ABABA 0X48002689 //MT29F16G08ABABA
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u8 NAND_Init(void);
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u8 NAND_ModeSet(u8 mode);
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u32 NAND_ReadID(void);
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u8 NAND_ReadStatus(void);
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u8 NAND_WaitForReady(void);
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u8 NAND_Reset(void);
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u8 NAND_WaitRB(vu8 rb);
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void NAND_Delay(vu32 i);
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u8 NAND_ReadPage(u32 PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToRead);
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u8 NAND_ReadPageComp(u32 PageNum,u16 ColNum,u32 CmpVal,u16 NumByteToRead,u16 *NumByteEqual);
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u8 NAND_WritePage(u32 PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToWrite);
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u8 NAND_WritePageConst(u32 PageNum,u16 ColNum,u32 cval,u16 NumByteToWrite);
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u8 NAND_CopyPageWithoutWrite(u32 Source_PageNum,u32 Dest_PageNum);
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u8 NAND_CopyPageWithWrite(u32 Source_PageNum,u32 Dest_PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToWrite);
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u8 NAND_ReadSpare(u32 PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToRead);
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u8 NAND_WriteSpare(u32 PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToRead);
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u8 NAND_EraseBlock(u32 BlockNum);
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void NAND_EraseChip(void);
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u16 NAND_ECC_Get_OE(u8 oe,u32 eccval);
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u8 NAND_ECC_Correction(u8* data_buf,u32 eccrd,u32 ecccl);
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#endif
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