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Qiea
2024-11-01 22:38:48 +08:00
parent 8dc9a9f472
commit a19f47efca
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157
HARDWARE/SDRAM/sdram.c Normal file
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#include "sdram.h"
#include "delay.h"
//////////////////////////////////////////////////////////////////////////////////
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>ѧϰʹ<CFB0>ã<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κ<EFBFBD><CEBA><EFBFBD>;
//ALIENTEK STM32F429<32><39><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:2016/1/6
//<2F>汾<EFBFBD><E6B1BE>V1.0
//<2F><>Ȩ<EFBFBD><C8A8><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ؾ<EFBFBD><D8BE><EFBFBD>
//Copyright(C) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾ 2014-2024
//All rights reserved
//////////////////////////////////////////////////////////////////////////////////
SDRAM_HandleTypeDef SDRAM_Handler; //SDRAM<41><4D><EFBFBD><EFBFBD>
//SDRAM<41><4D>ʼ<EFBFBD><CABC>
void SDRAM_Init(void)
{
FMC_SDRAM_TimingTypeDef SDRAM_Timing;
SDRAM_Handler.Instance=FMC_SDRAM_DEVICE; //SDRAM<41><4D>BANK5,6
SDRAM_Handler.Init.SDBank=FMC_SDRAM_BANK1; //SDRAM<41><4D><EFBFBD><EFBFBD>BANK5<4B><35>
SDRAM_Handler.Init.ColumnBitsNumber=FMC_SDRAM_COLUMN_BITS_NUM_9; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SDRAM_Handler.Init.RowBitsNumber=FMC_SDRAM_ROW_BITS_NUM_13; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SDRAM_Handler.Init.MemoryDataWidth=FMC_SDRAM_MEM_BUS_WIDTH_16; //<2F><><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>Ϊ16λ
SDRAM_Handler.Init.InternalBankNumber=FMC_SDRAM_INTERN_BANKS_NUM_4; //һ<><D2BB>4<EFBFBD><34>BANK
SDRAM_Handler.Init.CASLatency=FMC_SDRAM_CAS_LATENCY_3; //CASΪ3
SDRAM_Handler.Init.WriteProtection=FMC_SDRAM_WRITE_PROTECTION_DISABLE;//ʧ<><CAA7>д<EFBFBD><D0B4><EFBFBD><EFBFBD>
SDRAM_Handler.Init.SDClockPeriod=FMC_SDRAM_CLOCK_PERIOD_2; //SDRAMʱ<4D><CAB1>ΪHCLK/2=180M/2=90M=11.1ns
SDRAM_Handler.Init.ReadBurst=FMC_SDRAM_RBURST_ENABLE; //ʹ<><CAB9>ͻ<EFBFBD><CDBB>
SDRAM_Handler.Init.ReadPipeDelay=FMC_SDRAM_RPIPE_DELAY_1; //<2F><>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>ʱ
SDRAM_Timing.LoadToActiveDelay=2; //<2F><><EFBFBD><EFBFBD>ģʽ<C4A3>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ӳ<EFBFBD>Ϊ2<CEAA><32>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SDRAM_Timing.ExitSelfRefreshDelay=8; //<2F>˳<EFBFBD><CBB3><EFBFBD>ˢ<EFBFBD><CBA2><EFBFBD>ӳ<EFBFBD>Ϊ8<CEAA><38>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SDRAM_Timing.SelfRefreshTime=6; //<2F><>ˢ<EFBFBD><CBA2>ʱ<EFBFBD><CAB1>Ϊ6<CEAA><36>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SDRAM_Timing.RowCycleDelay=6; //<2F><>ѭ<EFBFBD><D1AD><EFBFBD>ӳ<EFBFBD>Ϊ6<CEAA><36>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SDRAM_Timing.WriteRecoveryTime=2; //<2F>ָ<EFBFBD><D6B8>ӳ<EFBFBD>Ϊ2<CEAA><32>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SDRAM_Timing.RPDelay=2; //<2F><>Ԥ<EFBFBD><D4A4><EFBFBD><EFBFBD><EFBFBD>ӳ<EFBFBD>Ϊ2<CEAA><32>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SDRAM_Timing.RCDDelay=2; //<2F>е<EFBFBD><D0B5><EFBFBD><EFBFBD>ӳ<EFBFBD>Ϊ2<CEAA><32>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
HAL_SDRAM_Init(&SDRAM_Handler,&SDRAM_Timing);
SDRAM_Initialization_Sequence(&SDRAM_Handler);//<2F><><EFBFBD><EFBFBD>SDRAM<41><4D>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}
//<2F><><EFBFBD><EFBFBD>SDRAM<41><4D>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram)
{
u32 temp=0;
//SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ժ<EFBFBD><D4BA><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˳<EFBFBD><CBB3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>SDRAM
SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_CLK_ENABLE,1,0); //ʱ<><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
delay_us(500); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ200us
SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_PALL,1,0); //<2F><><EFBFBD><EFBFBD><EFBFBD>д洢<D0B4><E6B4A2>Ԥ<EFBFBD><D4A4><EFBFBD><EFBFBD>
SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_AUTOREFRESH_MODE,8,0);//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˢ<EFBFBD>´<EFBFBD><C2B4><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ģʽ<C4A3>Ĵ<EFBFBD><C4B4><EFBFBD>,SDRAM<41><4D>bit0~bit2Ϊָ<CEAA><D6B8>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD>ʵij<CAB5><C4B3>ȣ<EFBFBD>
//bit3Ϊָ<CEAA><D6B8>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD>ͣ<EFBFBD>bit4~bit6ΪCASֵ<53><D6B5>bit7<74><37>bit8Ϊ<38><CEAA><EFBFBD><EFBFBD>ģʽ
//bit9Ϊָ<CEAA><D6B8><EFBFBD><EFBFBD>дͻ<D0B4><CDBB>ģʽ<C4A3><CABD>bit10<31><30>bit11λ<31><CEBB><EFBFBD><EFBFBD>λ
temp=(u32)SDRAM_MODEREG_BURST_LENGTH_1 | //<2F><><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:1(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1/2/4/8)
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | //<2F><><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD>)
SDRAM_MODEREG_CAS_LATENCY_3 | //<2F><><EFBFBD><EFBFBD>CASֵ:3(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2/3)
SDRAM_MODEREG_OPERATING_MODE_STANDARD | //<2F><><EFBFBD>ò<EFBFBD><C3B2><EFBFBD>ģʽ:0,<2C><>׼ģʽ
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; //<2F><><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB>дģʽ:1,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_LOAD_MODE,1,temp); //<2F><><EFBFBD><EFBFBD>SDRAM<41><4D>ģʽ<C4A3>Ĵ<EFBFBD><C4B4><EFBFBD>
//ˢ<><CBA2>Ƶ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>(<28><>SDCLKƵ<4B>ʼ<EFBFBD><CABC><EFBFBD>),<2C><><EFBFBD>㷽<EFBFBD><E3B7BD>:
//COUNT=SDRAMˢ<4D><CBA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD>-20=SDRAMˢ<4D><CBA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(us)*SDCLKƵ<4B><C6B5>(Mhz)/<2F><><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD>õ<EFBFBD>SDRAMˢ<4D><CBA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ64ms,SDCLK=180/2=90Mhz,<2C><><EFBFBD><EFBFBD>Ϊ8192(2^13).
//<2F><><EFBFBD><EFBFBD>,COUNT=64*1000*90/8192-20=683
HAL_SDRAM_ProgramRefreshRate(&SDRAM_Handler,683);
}
//SDRAM<41>ײ<EFBFBD><D7B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD>ʱ<EFBFBD><CAB1>ʹ<EFBFBD><CAB9>
//<2F>˺<EFBFBD><CBBA><EFBFBD><EFBFBD>ᱻHAL_SDRAM_Init()<29><><EFBFBD><EFBFBD>
//hsdram:SDRAM<41><4D><EFBFBD><EFBFBD>
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
{
GPIO_InitTypeDef GPIO_Initure;
__HAL_RCC_FMC_CLK_ENABLE(); //ʹ<><CAB9>FMCʱ<43><CAB1>
__HAL_RCC_GPIOC_CLK_ENABLE(); //ʹ<><CAB9>GPIOCʱ<43><CAB1>
__HAL_RCC_GPIOD_CLK_ENABLE(); //ʹ<><CAB9>GPIODʱ<44><CAB1>
__HAL_RCC_GPIOE_CLK_ENABLE(); //ʹ<><CAB9>GPIOEʱ<45><CAB1>
__HAL_RCC_GPIOF_CLK_ENABLE(); //ʹ<><CAB9>GPIOFʱ<46><CAB1>
__HAL_RCC_GPIOG_CLK_ENABLE(); //ʹ<><CAB9>GPIOGʱ<47><CAB1>
GPIO_Initure.Pin=GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_3;
GPIO_Initure.Mode=GPIO_MODE_AF_PP; //<2F><><EFBFBD>츴<EFBFBD><ECB8B4>
GPIO_Initure.Pull=GPIO_PULLUP; //<2F><><EFBFBD><EFBFBD>
GPIO_Initure.Speed=GPIO_SPEED_HIGH; //<2F><><EFBFBD><EFBFBD>
GPIO_Initure.Alternate=GPIO_AF12_FMC; //<2F><><EFBFBD><EFBFBD>ΪFMC
HAL_GPIO_Init(GPIOC,&GPIO_Initure); //<2F><>ʼ<EFBFBD><CABC>PC0,2,3
GPIO_Initure.Pin=GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14|GPIO_PIN_15;
HAL_GPIO_Init(GPIOD,&GPIO_Initure); //<2F><>ʼ<EFBFBD><CABC>PD0,1,8,9,10,14,15
GPIO_Initure.Pin=GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10| GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
HAL_GPIO_Init(GPIOE,&GPIO_Initure); //<2F><>ʼ<EFBFBD><CABC>PE0,1,7,8,9,10,11,12,13,14,15
GPIO_Initure.Pin=GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
HAL_GPIO_Init(GPIOF,&GPIO_Initure); //<2F><>ʼ<EFBFBD><CABC>PF0,1,2,3,4,5,11,12,13,14,15
GPIO_Initure.Pin=GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15;
HAL_GPIO_Init(GPIOG,&GPIO_Initure); //<2F><>ʼ<EFBFBD><CABC>PG0,1,2,4,5,8,15
}
//<2F><>SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//bankx:0,<2C><>BANK5<4B><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<41><4D><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
// 1,<2C><>BANK6<4B><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<41><4D><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
//cmd:ָ<><D6B8>(0,<2C><><EFBFBD><EFBFBD>ģʽ/1,ʱ<><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>/2,Ԥ<><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д洢<D0B4><E6B4A2>/3,<2C>Զ<EFBFBD>ˢ<EFBFBD><CBA2>/4,<2C><><EFBFBD><EFBFBD>ģʽ<C4A3>Ĵ<EFBFBD><C4B4><EFBFBD>/5,<2C><>ˢ<EFBFBD><CBA2>/6,<2C><><EFBFBD><EFBFBD>)
//refresh:<3A><>ˢ<EFBFBD>´<EFBFBD><C2B4><EFBFBD>
//regval:ģʽ<C4A3>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>Ķ<EFBFBD><C4B6><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ֵ:0,<2C><><EFBFBD><EFBFBD>;1,ʧ<><CAA7>.
u8 SDRAM_Send_Cmd(u8 bankx,u8 cmd,u8 refresh,u16 regval)
{
u32 target_bank=0;
FMC_SDRAM_CommandTypeDef Command;
if(bankx==0) target_bank=FMC_SDRAM_CMD_TARGET_BANK1;
else if(bankx==1) target_bank=FMC_SDRAM_CMD_TARGET_BANK2;
Command.CommandMode=cmd; //<2F><><EFBFBD><EFBFBD>
Command.CommandTarget=target_bank; //Ŀ<><C4BF>SDRAM<41>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD>
Command.AutoRefreshNumber=refresh; //<2F><>ˢ<EFBFBD>´<EFBFBD><C2B4><EFBFBD>
Command.ModeRegisterDefinition=regval; //Ҫд<D2AA><D0B4>ģʽ<C4A3>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ֵ
if(HAL_SDRAM_SendCommand(&SDRAM_Handler,&Command,0X1000)==HAL_OK) //<2F><>SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
{
return 0;
}
else return 1;
}
//<2F><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ַ(WriteAddr+Bank5_SDRAM_ADDR)<29><>ʼ,<2C><><EFBFBD><EFBFBD>д<EFBFBD><D0B4>n<EFBFBD><6E><EFBFBD>ֽ<EFBFBD>.
//pBuffer:<3A>ֽ<EFBFBD>ָ<EFBFBD><D6B8>
//WriteAddr:Ҫд<D2AA><D0B4><EFBFBD>ĵ<EFBFBD>ַ
//n:Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>
void FMC_SDRAM_WriteBuffer(u8 *pBuffer,u32 WriteAddr,u32 n)
{
for(;n!=0;n--)
{
*(vu8*)(Bank5_SDRAM_ADDR+WriteAddr)=*pBuffer;
WriteAddr++;
pBuffer++;
}
}
//<2F><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ַ((WriteAddr+Bank5_SDRAM_ADDR))<29><>ʼ,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>n<EFBFBD><6E><EFBFBD>ֽ<EFBFBD>.
//pBuffer:<3A>ֽ<EFBFBD>ָ<EFBFBD><D6B8>
//ReadAddr:Ҫ<><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
//n:Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>
void FMC_SDRAM_ReadBuffer(u8 *pBuffer,u32 ReadAddr,u32 n)
{
for(;n!=0;n--)
{
*pBuffer++=*(vu8*)(Bank5_SDRAM_ADDR+ReadAddr);
ReadAddr++;
}
}

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HARDWARE/SDRAM/sdram.h Normal file
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#ifndef _SDRAM_H
#define _SDRAM_H
#include "sys.h"
//////////////////////////////////////////////////////////////////////////////////
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>ѧϰʹ<CFB0>ã<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κ<EFBFBD><CEBA><EFBFBD>;
//ALIENTEK STM32F429<32><39><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:2016/1/6
//<2F>汾<EFBFBD><E6B1BE>V1.0
//<2F><>Ȩ<EFBFBD><C8A8><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ؾ<EFBFBD><D8BE><EFBFBD>
//Copyright(C) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾ 2014-2024
//All rights reserved
//////////////////////////////////////////////////////////////////////////////////
extern SDRAM_HandleTypeDef SDRAM_Handler;//SDRAM<41><4D><EFBFBD><EFBFBD>
#define Bank5_SDRAM_ADDR ((u32)(0XC0000000)) //SDRAM<41><4D>ʼ<EFBFBD><CABC>ַ
//SDRAM<41><4D><EFBFBD>ò<EFBFBD><C3B2><EFBFBD>
#define SDRAM_MODEREG_BURST_LENGTH_1 ((u16)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((u16)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((u16)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((u16)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((u16)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((u16)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((u16)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((u16)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((u16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((u16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((u16)0x0200)
void SDRAM_Init(void);
void SDRAM_MPU_Config(void);
u8 SDRAM_Send_Cmd(u8 bankx,u8 cmd,u8 refresh,u16 regval);
void FMC_SDRAM_WriteBuffer(u8 *pBuffer,u32 WriteAddr,u32 n);
void FMC_SDRAM_ReadBuffer(u8 *pBuffer,u32 ReadAddr,u32 n);
void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram);
#endif