The Firest Version
This commit is contained in:
Qiea
112
SYSTEM/sys/sys.c
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112
SYSTEM/sys/sys.c
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@@ -0,0 +1,112 @@
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#include "sys.h"
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//////////////////////////////////////////////////////////////////////////////////
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>ѧϰʹ<CFB0>ã<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κ<EFBFBD><CEBA><EFBFBD>;
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//ALIENTEK STM32F429<32><39><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC>
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//<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F>жϹ<D0B6><CFB9><EFBFBD>/GPIO<49><4F><EFBFBD>õ<EFBFBD>
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//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:2016/1/5
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//<2F>汾<EFBFBD><E6B1BE>V1.0
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//<2F><>Ȩ<EFBFBD><C8A8><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ؾ<EFBFBD><D8BE><EFBFBD>
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//Copyright(C) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾ 2014-2024
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//All rights reserved
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//********************************************************************************
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//<2F><EFBFBD>˵<EFBFBD><CBB5>
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//<2F><>
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//////////////////////////////////////////////////////////////////////////////////
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//ʱ<><CAB1>ϵͳ<CFB5><CDB3><EFBFBD>ú<EFBFBD><C3BA><EFBFBD>
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//Fvco=Fs*(plln/pllm);
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//SYSCLK=Fvco/pllp=Fs*(plln/(pllm*pllp));
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//Fusb=Fvco/pllq=Fs*(plln/(pllm*pllq));
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//Fvco:VCOƵ<4F><C6B5>
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//SYSCLK:ϵͳʱ<CDB3><CAB1>Ƶ<EFBFBD><C6B5>
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//Fusb:USB,SDIO,RNG<4E>ȵ<EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>
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//Fs:PLL<4C><4C><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HSI,HSE<53><45>.
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//plln:<3A><>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL<4C><4C>Ƶ),ȡֵ<C8A1><D6B5>Χ:64~432.
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//pllm:<3A><>PLL<4C><4C><EFBFBD><EFBFBD>ƵPLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮ǰ<D6AE>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~63.
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//pllp:ϵͳʱ<CDB3>ӵ<EFBFBD><D3B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2,4,6,8.(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><34>ֵ!)
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//pllq:USB/SDIO/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~15.
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//<2F>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD>Ϊ25M<35><4D>ʱ<EFBFBD><CAB1>,<2C>Ƽ<EFBFBD>ֵ:plln=360,pllm=25,pllp=2,pllq=8.
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//<2F>õ<EFBFBD>:Fvco=25*(360/25)=360Mhz
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// SYSCLK=360/2=180Mhz
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// Fusb=360/8=45Mhz
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//<2F><><EFBFBD><EFBFBD>ֵ:0,<2C>ɹ<EFBFBD>;1,ʧ<><CAA7>
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void Stm32_Clock_Init(u32 plln,u32 pllm,u32 pllp,u32 pllq)
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{
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HAL_StatusTypeDef ret = HAL_OK;
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RCC_OscInitTypeDef RCC_OscInitStructure;
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RCC_ClkInitTypeDef RCC_ClkInitStructure;
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__HAL_RCC_PWR_CLK_ENABLE(); //ʹ<><CAB9>PWRʱ<52><CAB1>
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD>
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//ʱʹ<CAB1><CAB9><EFBFBD><EFBFBD><EFBFBD>빦<EFBFBD><EBB9A6>ʵ<EFBFBD><CAB5>ƽ<EFBFBD>⣬<EFBFBD>˹<EFBFBD><CBB9><EFBFBD>ֻ<EFBFBD><D6BB>STM32F42xx<78><78>STM32F43xx<78><78><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);//<2F><><EFBFBD>õ<EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD>1
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RCC_OscInitStructure.OscillatorType=RCC_OSCILLATORTYPE_HSE; //ʱ<><CAB1>ԴΪHSE
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RCC_OscInitStructure.HSEState=RCC_HSE_ON; //<2F><><EFBFBD><EFBFBD>HSE
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RCC_OscInitStructure.PLL.PLLState=RCC_PLL_ON;//<2F><><EFBFBD><EFBFBD>PLL
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RCC_OscInitStructure.PLL.PLLSource=RCC_PLLSOURCE_HSE;//PLLʱ<4C><CAB1>Դѡ<D4B4><D1A1>HSE
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RCC_OscInitStructure.PLL.PLLM=pllm; //<2F><>PLL<4C><4C><EFBFBD><EFBFBD>ƵPLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮ǰ<D6AE>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~63.
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RCC_OscInitStructure.PLL.PLLN=plln; //<2F><>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL<4C><4C>Ƶ),ȡֵ<C8A1><D6B5>Χ:64~432.
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RCC_OscInitStructure.PLL.PLLP=pllp; //ϵͳʱ<CDB3>ӵ<EFBFBD><D3B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2,4,6,8.(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><34>ֵ!)
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RCC_OscInitStructure.PLL.PLLQ=pllq; //USB/SDIO/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~15.
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ret=HAL_RCC_OscConfig(&RCC_OscInitStructure);//<2F><>ʼ<EFBFBD><CABC>
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if(ret!=HAL_OK) while(1);
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ret=HAL_PWREx_EnableOverDrive(); //<2F><><EFBFBD><EFBFBD>Over-Driver<65><72><EFBFBD><EFBFBD>
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if(ret!=HAL_OK) while(1);
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//ѡ<><D1A1>PLL<4C><4C>Ϊϵͳʱ<CDB3><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HCLK,PCLK1<4B><31>PCLK2
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RCC_ClkInitStructure.ClockType=(RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStructure.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK;//<2F><><EFBFBD><EFBFBD>ϵͳʱ<CDB3><CAB1>ʱ<EFBFBD><CAB1>ԴΪPLL
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RCC_ClkInitStructure.AHBCLKDivider=RCC_SYSCLK_DIV1;//AHB<48><42>Ƶϵ<C6B5><CFB5>Ϊ1
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RCC_ClkInitStructure.APB1CLKDivider=RCC_HCLK_DIV4; //APB1<42><31>Ƶϵ<C6B5><CFB5>Ϊ4
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RCC_ClkInitStructure.APB2CLKDivider=RCC_HCLK_DIV2; //APB2<42><32>Ƶϵ<C6B5><CFB5>Ϊ2
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ret=HAL_RCC_ClockConfig(&RCC_ClkInitStructure,FLASH_LATENCY_5);//ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>FLASH<53><48>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ϊ5WS<57><53>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD>6<EFBFBD><36>CPU<50><55><EFBFBD>ڡ<EFBFBD>
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if(ret!=HAL_OK) while(1);
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}
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#ifdef USE_FULL_ASSERT
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>˺<EFBFBD><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//file<6C><65>ָ<EFBFBD><D6B8>Դ<EFBFBD>ļ<EFBFBD>
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//line<6E><65>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>е<EFBFBD><D0B5><EFBFBD><EFBFBD><EFBFBD>
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void assert_failed(uint8_t* file, uint32_t line)
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{
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while (1)
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{
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}
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}
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#endif
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//THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
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__asm void WFI_SET(void)
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{
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WFI;
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}
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//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>(<28><><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD>fault<6C><74>NMI<4D>ж<EFBFBD>)
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__asm void INTX_DISABLE(void)
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{
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CPSID I
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BX LR
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}
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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__asm void INTX_ENABLE(void)
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{
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CPSIE I
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BX LR
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}
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//<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ
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//addr:ջ<><D5BB><EFBFBD><EFBFBD>ַ
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__asm void MSR_MSP(u32 addr)
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{
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MSR MSP, r0 //set Main Stack value
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BX r14
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}
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132
SYSTEM/sys/sys.h
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132
SYSTEM/sys/sys.h
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@@ -0,0 +1,132 @@
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#ifndef _SYS_H
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#define _SYS_H
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#include "stm32f4xx.h"
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//////////////////////////////////////////////////////////////////////////////////
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>ѧϰʹ<CFB0>ã<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κ<EFBFBD><CEBA><EFBFBD>;
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//ALIENTEK STM32F429<32><39><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC>
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//<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F>жϹ<D0B6><CFB9><EFBFBD>/GPIO<49><4F><EFBFBD>õ<EFBFBD>
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//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:2015/6/10
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//<2F>汾<EFBFBD><E6B1BE>V1.0
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//<2F><>Ȩ<EFBFBD><C8A8><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ؾ<EFBFBD><D8BE><EFBFBD>
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//Copyright(C) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾ 2014-2024
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//All rights reserved
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//********************************************************************************
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//<2F><EFBFBD>˵<EFBFBD><CBB5>
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//<2F><>
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//////////////////////////////////////////////////////////////////////////////////
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//0,<2C><>֧<EFBFBD><D6A7>os
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//1,֧<><D6A7>os
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#define SYSTEM_SUPPORT_OS 0 //<2F><><EFBFBD><EFBFBD>ϵͳ<CFB5>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD>Ƿ<EFBFBD>֧<EFBFBD><D6A7>OS
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///////////////////////////////////////////////////////////////////////////////////
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//<2F><><EFBFBD><EFBFBD>һЩ<D2BB><D0A9><EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͷ̹ؼ<CCB9><D8BC><EFBFBD>
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typedef int32_t s32;
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typedef int16_t s16;
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typedef int8_t s8;
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typedef const int32_t sc32;
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typedef const int16_t sc16;
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typedef const int8_t sc8;
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typedef __IO int32_t vs32;
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typedef __IO int16_t vs16;
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typedef __IO int8_t vs8;
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typedef __I int32_t vsc32;
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typedef __I int16_t vsc16;
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typedef __I int8_t vsc8;
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef const uint32_t uc32;
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typedef const uint16_t uc16;
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typedef const uint8_t uc8;
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typedef __IO uint32_t vu32;
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typedef __IO uint16_t vu16;
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typedef __IO uint8_t vu8;
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typedef __I uint32_t vuc32;
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typedef __I uint16_t vuc16;
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typedef __I uint8_t vuc8;
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//λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,ʵ<><CAB5>51<35><31><EFBFBD>Ƶ<EFBFBD>GPIO<49><4F><EFBFBD>ƹ<EFBFBD><C6B9><EFBFBD>
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//<2F><><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5>˼<EFBFBD><CBBC>,<2C>ο<EFBFBD><<CM3Ȩ<33><C8A8>ָ<EFBFBD><D6B8>>><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(87ҳ~92ҳ).M4ͬM3<4D><33><EFBFBD><EFBFBD>,ֻ<>ǼĴ<C7BC><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>.
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//IO<49>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD>궨<EFBFBD><EAB6A8>
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#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
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#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
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#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
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//IO<49>ڵ<EFBFBD>ַӳ<D6B7><D3B3>
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#define GPIOA_ODR_Addr (GPIOA_BASE+20) //0x40020014
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#define GPIOB_ODR_Addr (GPIOB_BASE+20) //0x40020414
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#define GPIOC_ODR_Addr (GPIOC_BASE+20) //0x40020814
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#define GPIOD_ODR_Addr (GPIOD_BASE+20) //0x40020C14
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#define GPIOE_ODR_Addr (GPIOE_BASE+20) //0x40021014
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#define GPIOF_ODR_Addr (GPIOF_BASE+20) //0x40021414
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#define GPIOG_ODR_Addr (GPIOG_BASE+20) //0x40021814
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#define GPIOH_ODR_Addr (GPIOH_BASE+20) //0x40021C14
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#define GPIOI_ODR_Addr (GPIOI_BASE+20) //0x40022014
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#define GPIOJ_ODR_ADDr (GPIOJ_BASE+20) //0x40022414
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#define GPIOK_ODR_ADDr (GPIOK_BASE+20) //0x40022814
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#define GPIOA_IDR_Addr (GPIOA_BASE+16) //0x40020010
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#define GPIOB_IDR_Addr (GPIOB_BASE+16) //0x40020410
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#define GPIOC_IDR_Addr (GPIOC_BASE+16) //0x40020810
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#define GPIOD_IDR_Addr (GPIOD_BASE+16) //0x40020C10
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#define GPIOE_IDR_Addr (GPIOE_BASE+16) //0x40021010
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#define GPIOF_IDR_Addr (GPIOF_BASE+16) //0x40021410
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#define GPIOG_IDR_Addr (GPIOG_BASE+16) //0x40021810
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#define GPIOH_IDR_Addr (GPIOH_BASE+16) //0x40021C10
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#define GPIOI_IDR_Addr (GPIOI_BASE+16) //0x40022010
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#define GPIOJ_IDR_Addr (GPIOJ_BASE+16) //0x40022410
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#define GPIOK_IDR_Addr (GPIOK_BASE+16) //0x40022810
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//IO<49>ڲ<EFBFBD><DAB2><EFBFBD>,ֻ<>Ե<EFBFBD>һ<EFBFBD><D2BB>IO<49><4F>!
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//ȷ<><C8B7>n<EFBFBD><6E>ֵС<D6B5><D0A1>16!
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#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PHout(n) BIT_ADDR(GPIOH_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PHin(n) BIT_ADDR(GPIOH_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PIout(n) BIT_ADDR(GPIOI_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PIin(n) BIT_ADDR(GPIOI_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PJout(n) BIT_ADDR(GPIOJ_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PJin(n) BIT_ADDR(GPIOJ_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PKout(n) BIT_ADDR(GPIOK_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PKin(n) BIT_ADDR(GPIOK_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
void Stm32_Clock_Init(u32 plln,u32 pllm,u32 pllp,u32 pllq);//ʱ<><CAB1>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD>ຯ<EFBFBD><E0BAAF>
|
||||
void WFI_SET(void); //ִ<><D6B4>WFIָ<49><D6B8>
|
||||
void INTX_DISABLE(void);//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
void INTX_ENABLE(void); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
void MSR_MSP(u32 addr); //<2F><><EFBFBD>ö<EFBFBD>ջ<EFBFBD><D5BB>ַ
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user