The Firest Version
This commit is contained in:
112
SYSTEM/sys/sys.c
Normal file
112
SYSTEM/sys/sys.c
Normal file
@@ -0,0 +1,112 @@
|
||||
#include "sys.h"
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>ѧϰʹ<CFB0>ã<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κ<EFBFBD><CEBA><EFBFBD>;
|
||||
//ALIENTEK STM32F429<32><39><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC>
|
||||
//<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F>жϹ<D0B6><CFB9><EFBFBD>/GPIO<49><4F><EFBFBD>õ<EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:2016/1/5
|
||||
//<2F>汾<EFBFBD><E6B1BE>V1.0
|
||||
//<2F><>Ȩ<EFBFBD><C8A8><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ؾ<EFBFBD><D8BE><EFBFBD>
|
||||
//Copyright(C) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾ 2014-2024
|
||||
//All rights reserved
|
||||
//********************************************************************************
|
||||
//<2F><EFBFBD>˵<EFBFBD><CBB5>
|
||||
//<2F><>
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//ʱ<><CAB1>ϵͳ<CFB5><CDB3><EFBFBD>ú<EFBFBD><C3BA><EFBFBD>
|
||||
//Fvco=Fs*(plln/pllm);
|
||||
//SYSCLK=Fvco/pllp=Fs*(plln/(pllm*pllp));
|
||||
//Fusb=Fvco/pllq=Fs*(plln/(pllm*pllq));
|
||||
|
||||
//Fvco:VCOƵ<4F><C6B5>
|
||||
//SYSCLK:ϵͳʱ<CDB3><CAB1>Ƶ<EFBFBD><C6B5>
|
||||
//Fusb:USB,SDIO,RNG<4E>ȵ<EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>
|
||||
//Fs:PLL<4C><4C><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HSI,HSE<53><45>.
|
||||
//plln:<3A><>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL<4C><4C>Ƶ),ȡֵ<C8A1><D6B5>Χ:64~432.
|
||||
//pllm:<3A><>PLL<4C><4C><EFBFBD><EFBFBD>ƵPLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮ǰ<D6AE>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~63.
|
||||
//pllp:ϵͳʱ<CDB3>ӵ<EFBFBD><D3B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2,4,6,8.(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><34>ֵ!)
|
||||
//pllq:USB/SDIO/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~15.
|
||||
|
||||
//<2F>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD>Ϊ25M<35><4D>ʱ<EFBFBD><CAB1>,<2C>Ƽ<EFBFBD>ֵ:plln=360,pllm=25,pllp=2,pllq=8.
|
||||
//<2F>õ<EFBFBD>:Fvco=25*(360/25)=360Mhz
|
||||
// SYSCLK=360/2=180Mhz
|
||||
// Fusb=360/8=45Mhz
|
||||
//<2F><><EFBFBD><EFBFBD>ֵ:0,<2C>ɹ<EFBFBD>;1,ʧ<><CAA7>
|
||||
void Stm32_Clock_Init(u32 plln,u32 pllm,u32 pllp,u32 pllq)
|
||||
{
|
||||
HAL_StatusTypeDef ret = HAL_OK;
|
||||
RCC_OscInitTypeDef RCC_OscInitStructure;
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStructure;
|
||||
|
||||
__HAL_RCC_PWR_CLK_ENABLE(); //ʹ<><CAB9>PWRʱ<52><CAB1>
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD>
|
||||
//ʱʹ<CAB1><CAB9><EFBFBD><EFBFBD><EFBFBD>빦<EFBFBD><EBB9A6>ʵ<EFBFBD><CAB5>ƽ<EFBFBD>⣬<EFBFBD>˹<EFBFBD><CBB9><EFBFBD>ֻ<EFBFBD><D6BB>STM32F42xx<78><78>STM32F43xx<78><78><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);//<2F><><EFBFBD>õ<EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD>1
|
||||
|
||||
RCC_OscInitStructure.OscillatorType=RCC_OSCILLATORTYPE_HSE; //ʱ<><CAB1>ԴΪHSE
|
||||
RCC_OscInitStructure.HSEState=RCC_HSE_ON; //<2F><><EFBFBD><EFBFBD>HSE
|
||||
RCC_OscInitStructure.PLL.PLLState=RCC_PLL_ON;//<2F><><EFBFBD><EFBFBD>PLL
|
||||
RCC_OscInitStructure.PLL.PLLSource=RCC_PLLSOURCE_HSE;//PLLʱ<4C><CAB1>Դѡ<D4B4><D1A1>HSE
|
||||
RCC_OscInitStructure.PLL.PLLM=pllm; //<2F><>PLL<4C><4C><EFBFBD><EFBFBD>ƵPLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮ǰ<D6AE>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~63.
|
||||
RCC_OscInitStructure.PLL.PLLN=plln; //<2F><>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL<4C><4C>Ƶ),ȡֵ<C8A1><D6B5>Χ:64~432.
|
||||
RCC_OscInitStructure.PLL.PLLP=pllp; //ϵͳʱ<CDB3>ӵ<EFBFBD><D3B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2,4,6,8.(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><34>ֵ!)
|
||||
RCC_OscInitStructure.PLL.PLLQ=pllq; //USB/SDIO/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~15.
|
||||
ret=HAL_RCC_OscConfig(&RCC_OscInitStructure);//<2F><>ʼ<EFBFBD><CABC>
|
||||
|
||||
if(ret!=HAL_OK) while(1);
|
||||
|
||||
ret=HAL_PWREx_EnableOverDrive(); //<2F><><EFBFBD><EFBFBD>Over-Driver<65><72><EFBFBD><EFBFBD>
|
||||
if(ret!=HAL_OK) while(1);
|
||||
|
||||
//ѡ<><D1A1>PLL<4C><4C>Ϊϵͳʱ<CDB3><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HCLK,PCLK1<4B><31>PCLK2
|
||||
RCC_ClkInitStructure.ClockType=(RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStructure.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK;//<2F><><EFBFBD><EFBFBD>ϵͳʱ<CDB3><CAB1>ʱ<EFBFBD><CAB1>ԴΪPLL
|
||||
RCC_ClkInitStructure.AHBCLKDivider=RCC_SYSCLK_DIV1;//AHB<48><42>Ƶϵ<C6B5><CFB5>Ϊ1
|
||||
RCC_ClkInitStructure.APB1CLKDivider=RCC_HCLK_DIV4; //APB1<42><31>Ƶϵ<C6B5><CFB5>Ϊ4
|
||||
RCC_ClkInitStructure.APB2CLKDivider=RCC_HCLK_DIV2; //APB2<42><32>Ƶϵ<C6B5><CFB5>Ϊ2
|
||||
ret=HAL_RCC_ClockConfig(&RCC_ClkInitStructure,FLASH_LATENCY_5);//ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>FLASH<53><48>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ϊ5WS<57><53>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD>6<EFBFBD><36>CPU<50><55><EFBFBD>ڡ<EFBFBD>
|
||||
|
||||
if(ret!=HAL_OK) while(1);
|
||||
}
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>˺<EFBFBD><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//file<6C><65>ָ<EFBFBD><D6B8>Դ<EFBFBD>ļ<EFBFBD>
|
||||
//line<6E><65>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>е<EFBFBD><D0B5><EFBFBD><EFBFBD><EFBFBD>
|
||||
void assert_failed(uint8_t* file, uint32_t line)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
//THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
|
||||
__asm void WFI_SET(void)
|
||||
{
|
||||
WFI;
|
||||
}
|
||||
//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>(<28><><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD>fault<6C><74>NMI<4D>ж<EFBFBD>)
|
||||
__asm void INTX_DISABLE(void)
|
||||
{
|
||||
CPSID I
|
||||
BX LR
|
||||
}
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
__asm void INTX_ENABLE(void)
|
||||
{
|
||||
CPSIE I
|
||||
BX LR
|
||||
}
|
||||
//<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ
|
||||
//addr:ջ<><D5BB><EFBFBD><EFBFBD>ַ
|
||||
__asm void MSR_MSP(u32 addr)
|
||||
{
|
||||
MSR MSP, r0 //set Main Stack value
|
||||
BX r14
|
||||
}
|
||||
Reference in New Issue
Block a user